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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">PnR Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">PnR Summaries</a></li>-->
<li><a href="#PnR_Details" style=" font-size: 16px;">PnR Details</a>
<li><a href="#Resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#Resource_Usage_Summary" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#I/O_Bank_Usage_Summary" style=" font-size: 14px;">I/O Bank Usage Summary</a></li>
<li><a href="#Global_Clock_Usage_Summary" style=" font-size: 14px;">Clock Resource Usage Summary</a></li>
<li><a href="#Global_Clock_Signals" style=" font-size: 14px;">Global Clock Signals</a></li>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
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<div id="content">
<h1><a name="Message">PnR Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>PnR Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\lab\lab1\impl\gwsynthesis\lab1.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\lab\lab1\src\lab1.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11.01 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2AR-LV18QN88C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2AR-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jun 19 21:21:19 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="PnR_Details">PnR Details</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<table class="summary_table">
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
   Placement Phase 0: CPU time = 0h 0m 0.027s, Elapsed time = 0h 0m 0.027s
   Placement Phase 1: CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.403s
   Placement Phase 2: CPU time = 0h 0m 0.023s, Elapsed time = 0h 0m 0.024s
   Placement Phase 3: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.593s
   Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Running routing:
   Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
   Routing Phase 1: CPU time = 0h 0m 0.142s, Elapsed time = 0h 0m 0.143s
   Routing Phase 2: CPU time = 0h 0m 0.134s, Elapsed time = 0h 0m 0.134s
   Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
   Total Routing: CPU time = 0h 0m 0.277s, Elapsed time = 0h 0m 0.278s
Generate output files:
   CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 479MB</td>
</tr>
</table>
<br/>
<h1><a name="Resource">Resource</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>33/20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>33(9 LUT, 24 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --SSRAM(RAM16)</td>
<td>0</td>
<td>-</td>
</tr>
<tr>
<td class="label">Register</td>
<td>26/15750</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
<td>0/15552</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>26/15552</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
<td>0/198</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as FF</td>
<td>0/198</td>
<td>0%</td>
</tr>
<tr>
<td class="label">CLS</td>
<td>19/10368</td>
<td><1%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>2/66</td>
<td>4%</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>2</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>1</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>1</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Inout Buf</td>
<td>0</td>
<td>-</td>
</tr>
</table>
<h2><a name="I/O_Bank_Usage_Summary">I/O Bank Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>I/O Bank</b></td>
<td><b>Usage</b></td><td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">bank 0</td>
<td>0/8</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 1</td>
<td>0/9</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 2</td>
<td>0/4</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 3</td>
<td>0/17</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 4</td>
<td>0/8</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 5</td>
<td>0/10</td><td>0%</td>
</tr>
<tr>
<td class="label">bank 6</td>
<td>1/9</td><td>12%</td>
</tr>
<tr>
<td class="label">bank 7</td>
<td>1/1</td><td>100%</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Usage_Summary">Clock Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Clock Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>1/8</td>
<td>13%</td>
</tr>
<tr>
<td class="label">LW</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
<td>0/5</td>
<td>0%</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Signal</b></td>
<td><b>Global Clock</b></td>
<td><b>Location</b></td>
</tr>
<tr>
<td class="label">Clock_d</td>
<td>PRIMARY</td>
<td> TR TL BL</td>
</tr>
</table>
<br/>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>CFG</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">Clock</td>
<td>-</td>
<td>4/7</td>
<td>Y</td>
<td>in</td>
<td>IOL7[A]</td>
<td>LPLL1_T_in</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">IO_voltage</td>
<td>-</td>
<td>15/6</td>
<td>Y</td>
<td>out</td>
<td>IOL47[A]</td>
<td>LPLL2_T_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>CFG</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">86/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">85/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">84/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">83/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">82/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">81/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">80/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[A]</td>
<td>GCLKT_0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">79/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[B]</td>
<td>GCLKC_0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">77/1</td>
<td>-</td>
<td>in</td>
<td>IOT30[A]</td>
<td>GCLKT_1</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">76/1</td>
<td>-</td>
<td>in</td>
<td>IOT30[B]</td>
<td>GCLKC_1</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">75/1</td>
<td>-</td>
<td>in</td>
<td>IOT34[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">74/1</td>
<td>-</td>
<td>in</td>
<td>IOT34[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">73/1</td>
<td>-</td>
<td>in</td>
<td>IOT40[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">72/1</td>
<td>-</td>
<td>in</td>
<td>IOT40[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">71/1</td>
<td>-</td>
<td>in</td>
<td>IOT44[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">70/1</td>
<td>-</td>
<td>in</td>
<td>IOT44[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">69/1</td>
<td>-</td>
<td>in</td>
<td>IOT50[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">25/5</td>
<td>-</td>
<td>in</td>
<td>IOB6[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">26/5</td>
<td>-</td>
<td>in</td>
<td>IOB6[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">27/5</td>
<td>-</td>
<td>in</td>
<td>IOB8[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">28/5</td>
<td>-</td>
<td>in</td>
<td>IOB8[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">29/5</td>
<td>-</td>
<td>in</td>
<td>IOB14[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">30/5</td>
<td>-</td>
<td>in</td>
<td>IOB14[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">31/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">32/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">33/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">34/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">35/4</td>
<td>-</td>
<td>in</td>
<td>IOB30[A]</td>
<td>GCLKT_4</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">36/4</td>
<td>-</td>
<td>in</td>
<td>IOB30[B]</td>
<td>GCLKC_4</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">37/4</td>
<td>-</td>
<td>in</td>
<td>IOB34[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">38/4</td>
<td>-</td>
<td>in</td>
<td>IOB34[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">39/4</td>
<td>-</td>
<td>in</td>
<td>IOB40[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">40/4</td>
<td>-</td>
<td>in</td>
<td>IOB40[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">42/4</td>
<td>-</td>
<td>in</td>
<td>IOB42[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">41/4</td>
<td>-</td>
<td>in</td>
<td>IOB43[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">p1/7</td>
<td>-</td>
<td>in</td>
<td>IOL3[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p2/7</td>
<td>-</td>
<td>in</td>
<td>IOL3[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">4/7</td>
<td>Clock</td>
<td>in</td>
<td>IOL7[A]</td>
<td>LPLL1_T_in</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p5/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[A]</td>
<td>LPLL1_T_fb</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p6/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[B]</td>
<td>LPLL1_C_fb</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p7/7</td>
<td>-</td>
<td>in</td>
<td>IOL9[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p8/7</td>
<td>-</td>
<td>in</td>
<td>IOL9[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p11/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p12/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p14/7</td>
<td>-</td>
<td>in</td>
<td>IOL12[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p19/7</td>
<td>-</td>
<td>in</td>
<td>IOL12[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p18/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p21/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p20/7</td>
<td>-</td>
<td>in</td>
<td>IOL14[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p22/7</td>
<td>-</td>
<td>in</td>
<td>IOL14[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p23/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p24/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p26/7</td>
<td>-</td>
<td>in</td>
<td>IOL16[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p28/7</td>
<td>-</td>
<td>in</td>
<td>IOL16[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p25/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p27/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p29/7</td>
<td>-</td>
<td>in</td>
<td>IOL18[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p31/7</td>
<td>-</td>
<td>in</td>
<td>IOL18[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p32/7</td>
<td>-</td>
<td>in</td>
<td>IOL20[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">10/6</td>
<td>-</td>
<td>in</td>
<td>IOL29[A]</td>
<td>GCLKT_6</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">11/6</td>
<td>-</td>
<td>in</td>
<td>IOL29[B]</td>
<td>GCLKC_6</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p35/6</td>
<td>-</td>
<td>in</td>
<td>IOL30[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p36/6</td>
<td>-</td>
<td>in</td>
<td>IOL30[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p37/6</td>
<td>-</td>
<td>in</td>
<td>IOL35[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p38/6</td>
<td>-</td>
<td>in</td>
<td>IOL35[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p41/6</td>
<td>-</td>
<td>in</td>
<td>IOL39[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p42/6</td>
<td>-</td>
<td>in</td>
<td>IOL39[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">13/6</td>
<td>-</td>
<td>in</td>
<td>IOL45[A]</td>
<td>LPLL2_T_in</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">15/6</td>
<td>IO_voltage</td>
<td>out</td>
<td>IOL47[A]</td>
<td>LPLL2_T_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">16/6</td>
<td>-</td>
<td>in</td>
<td>IOL47[B]</td>
<td>LPLL2_C_fb</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">17/6</td>
<td>-</td>
<td>in</td>
<td>IOL49[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">18/6</td>
<td>-</td>
<td>in</td>
<td>IOL49[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">19/6</td>
<td>-</td>
<td>in</td>
<td>IOL51[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">20/6</td>
<td>-</td>
<td>in</td>
<td>IOL51[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p89/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p88/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p85/2</td>
<td>-</td>
<td>in</td>
<td>IOR4[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p84/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p82/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p83/2</td>
<td>-</td>
<td>in</td>
<td>IOR6[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p79/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p78/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p76/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p73/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p70/2</td>
<td>-</td>
<td>in</td>
<td>IOR12[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p68/2</td>
<td>-</td>
<td>in</td>
<td>IOR12[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p69/2</td>
<td>-</td>
<td>in</td>
<td>IOR13[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p66/2</td>
<td>-</td>
<td>in</td>
<td>IOR13[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p67/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p65/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p64/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p61/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p58/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p55/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p59/2</td>
<td>-</td>
<td>in</td>
<td>IOR17[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p54/2</td>
<td>-</td>
<td>in</td>
<td>IOR17[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p53/2</td>
<td>-</td>
<td>in</td>
<td>IOR18[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p52/2</td>
<td>-</td>
<td>in</td>
<td>IOR18[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">8/2</td>
<td>-</td>
<td>out</td>
<td>IOR25[A]</td>
<td>TDO</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">5/2</td>
<td>-</td>
<td>in</td>
<td>IOR25[B]</td>
<td>TMS</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">6/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[A]</td>
<td>TCK</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">7/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[B]</td>
<td>TDI</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">63/3</td>
<td>-</td>
<td>in</td>
<td>IOR29[A]</td>
<td>GCLKT_3</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">88/3</td>
<td>-</td>
<td>in</td>
<td>IOR30[A]</td>
<td>MODE0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">87/3</td>
<td>-</td>
<td>in</td>
<td>IOR30[B]</td>
<td>MODE1</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">9/3</td>
<td>-</td>
<td>in</td>
<td>IOR31[B]</td>
<td>RECONFIG_N</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">62/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[A]</td>
<td>MI/D7</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">61/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[B]</td>
<td>MO/D6</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">60/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[A]</td>
<td>MCS_N/D5</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">59/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[B]</td>
<td>MCLK/D4</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">57/3</td>
<td>-</td>
<td>in</td>
<td>IOR35[A]</td>
<td>FASTRD_N/D3</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">56/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[A]</td>
<td>SO/D1</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">55/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[B]</td>
<td>SSPI_CS_N/D0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">54/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[A]</td>
<td>DIN/CLKHOLD_N</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">53/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[B]</td>
<td>DOUT/WE_N</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">52/3</td>
<td>-</td>
<td>in</td>
<td>IOR39[A]</td>
<td>SCLK</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p49/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p48/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">51/3</td>
<td>-</td>
<td>in</td>
<td>IOR45[A]</td>
<td>RPLL2_T_in</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">49/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">48/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
<br/>
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